Silicon-based ultralarge-scale integrated (ULSI) circuitry is one of infra-technologies that support advanced information society in near future. For further functional improvement of ULSI circuits, it is inevitable to enhance performances of MISFETs, which are major elements of ULSI circuit devices. Traditionally the performance enhancement of on-chip circuit elements has fundamentally relied upon miniaturization and downscaling rules—i.e., proportional shrinkage of minimum feature sizes. In recent years, however, it is likely that this approach has almost reached physical limits and thus is faced with difficulties not only in achieving higher performances of circuit elements by miniaturization but also in retaining proper operations of such downscaled circuit elements per se.
One of such physical limits is a problem of parasitic resistance of source/drain (S/D) region. See FIG. 47, which shows a typical structure of prior known MISFET. As shown herein, a silicide film 110 is formed at S/D electrode, with a Schottky junction being formed between this silicide film 110 on one hand and a heavily-doped diffusion layer 108 around silicide 110 and its associated extension diffusion 105 on the other hand. In this case, the parasitic resistance of S/D electrode consists essentially of three resistance components: the silicide film 110's own resistance Rs, the heavily-doped layer 108's resistance Rd which is the so-called bulk film resistance, and the junction's interface resistance Rc.
Regarding the silicide film's own resistance Rs, the recent trend is to use a nickel silicide (NiSi) film, which is less in resistance than traditional titanium silicide (TiSi2) and cobalt silicide (CoSi2) films. This NiSi film is a technically attractive material owing to its advantages in addition to the low resistance: fabrication capability at low temperatures, shallow film formability with less consumption of silicon (Si) during silicidation, and usability as silicides for both N-channel and P-channel FETs due to the fact that the NiSi's work function is in close proximity to a mid gap of the energy bands of Si.
For reduction of the junction interface resistance Rc, it is known that it is important to increase the concentration of a doped impurity at the interface between the silicide film 110 and the heavily-doped Si layer 108 in the MISFET of FIG. 47. See FIG. 48, which is a band diagram of Schottky junction to be formed between silicide and heavily-doped Si films. An electron moves or “migrates” between these films by tunneling a peak of energy equivalent to the height of such Schottky barrier. The tunnel ability of this electron is generally called the tunnel probability among those skilled in the art. The higher the tunnel probability of junction interface, the lower the interface resistance.
It is also known that the tunnel probability decreases exponentially relative to a product of Schottky barrier height and tunneling distance. Reducing the Schottky barrier height and tunnel distance leads to a decrease in interface resistance. By increasing the impurity concentration at the interface between the silicide film and heavily-doped Si layer, the tunnel distance decreases due to occurrence of an effect for enhancing the curvature of Si layer band as shown in FIG. 49. And when image charge effect being taken into consideration, the Schottky barrier height per se is also reduced as apparent from FIG. 49. Obviously this results in a decrease in the product of Schottky barrier height and tunnel distance, thus reducing the interface resistance Rc.
One known NiSi layer forming process is shown in FIG. 50. This process includes the steps of forming in Si layer a pair of source/drain (S/D) diffusion regions and thereafter sputtering Ni onto these S/D regions for silicidation. Unfortunately this prior art process suffers from difficulty in increasing the impurity concentration at the interface between the silicide film 110 and heavily-doped Si layer 108—in particular, in the case of p-type Si.
Turning to FIGS. 51A and 51B, each graph shows a secondary ion mass spectroscopy (SIMS) observation result of the interface between a NiSi layer and heavily-doped Si layer as has been formed by the process shown in FIG. 50. As can be seen from FIG. 51A, in the case of an arsenic (As) dopant that is an n-type impurity for Si, a distribution of impurity concentration expands on both sides of the interface. In contrast, as shown in FIG. 51B, a p-type impurity doped—e.g., boron (B)—is distributed mostly within NiSi film, with its concentration on the Si side being extremely lowered. This is because B impurity is taken into NiSi film during silicidation. As apparent from the observation results, it remains difficult for prior art NiSi layer formation processes to reduce the junction interface resistance Rc.
From the viewpoint of performance enhancement of MISFETs as required by the proportional downscaling rules for ULSI chips, it is also important to improve the carrier mobility of the channel region underlying the insulated gate electrode. Regarding this, new types of transistor structures have been proposed until today. Especially, for P-channel MISFETs (PMISFETs) having high impurity concentration S/D regions with an acceptor being doped thereinto, the promising approach is to use a device structure having its S/D regions in which silicon germanium (SixGe1-x, where the suffix “x” is zero or a positive number less than one) is buried, as taught from P. Ranade et al., “High Performance 35 nm LGATE CMOS Transistors Featuring NiSi Metal Gate (FUSI), Uniaxial Strained Silicon Channels and 1.2 nm Gate Oxide,” Technical Digest of the International Electron and Devices Meeting, IEDM 2005, paper 10.1, pp 227-230. It is known that use of this device structure leads to improvements in carrier mobility because the channel region is applied a stress due to a deviation of lattice constant between Si and SiGe layers.
As apparent from the foregoing description, in order to improve the MISFET characteristics, a need is felt to provide a device structure and its fabrication process for lowering the electrical resistance of the interface of a heavily-doped layer and its associated metal silicide layer in S/D region of MISFET. In particular, in order to enhance the carrier mobility, it has been demanded to develop a new and improved semiconductor device best suited to the MISFET with the strain-added channel region along with a fabrication process thereof.